Browse Prior Art Database

Dual Bit Switching Network for Read Only Memory Systems

IP.com Disclosure Number: IPCOM000051923D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Selleck, JE: AUTHOR [+2]

Abstract

By using a dual-bit switching network for read-only memories as illustr in the figure, optimum sense amplifier performance can be achieved with reduced requirements for silicon substrate area.

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Dual Bit Switching Network for Read Only Memory Systems

By using a dual-bit switching network for read-only memories as illustr in the figure, optimum sense amplifier performance can be achieved with reduced requirements for silicon substrate area.

With the dual-bit switching network 10 incorporated into the read-only memory system shown in the figure, an improved read-only memory system is provided over that disclosed in IBM Technical Disclosure Bulletin 23, 2250-2254 (November 1980). In the figure, column decoder 14 and column drivers 12, producing pulses on lines CS0, CS1, CS2 and CS3, may be similar to the column decoder 14 and column driver 12 illustrated in the above-cited article. The memory array 16, having a word line WL to which sixteen field-effect transistors T1 to T16 are coupled, may be similar to the array in the cited article which includes word line WL and transistors TC10, TC12, TC14 and TC16 for storing binary information. Of course, although only one word line is illustrated, it should be understood that the array may, preferably, have hundreds of parallel arranged word lines, and hundreds of transistors may, if desired, be coupled to each word line.

The memory system illustrated in the figure shows one word line with four decoded column addresses, CS0, CS1, CS2 and CS3, applied from column decoder 14 via lines CS0, CS1, CS2 and CS3 to column drivers or inverters 12 producing complementary addresses CS0, CS1, CS2 and CS3. The figure also shows four-bit outputs corresponding to each column address. Accordingly, there are four words times four bits per word for a total of 16 bits. The fan-out is equal to two for each column address, except for address CS0.

In the operation of the system, only one column decoder out of the four column decoders is selected at a time. Each column decoder enables two column select lines, e.g., lines L1 and L2 connected to line CS2 and each column line, e.g., line L1, enables two bit lines, BL1 and BL0. One bit of information such as from bit line BL1 connected to the common...