Browse Prior Art Database

Shared Contact Non Volatile Device Cells

IP.com Disclosure Number: IPCOM000051927D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Kalter, HL: AUTHOR [+2]

Abstract

Non-volatile device cells, using effectively a known dual-gate electrically erasable read-only memory cell having enhanced conduction doped insulators, are arranged so that contacts are shared by a plurality of cells. Enhanced conduction doped insulators are described in U. S. Patents 3,972,059 and 4,104,675.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 2

Shared Contact Non Volatile Device Cells

Non-volatile device cells, using effectively a known dual-gate electrically erasable read-only memory cell having enhanced conduction doped insulators, are arranged so that contacts are shared by a plurality of cells. Enhanced conduction doped insulators are described in U. S. Patents 3,972,059 and 4,104,675.

As illustrated in Figs. 1, 2 and 3, the structure includes a P-type semiconductor substrate 10 having an insulating layer of silicon dioxide 12 disposed thereon and first and second Ndiffusions 14 and 16 formed therein. A first layer of doped polysilicon is deposited on insulating layer 12, and a floating gate electrode 18 is formed therefrom with the use of a silicon nitride mask. A second layer of doped polysilicon is then blanket deposited, and a first gate electrode G1 is formed therefrom and oxidized to form insulating layer 21. By using a known dip etch technique, the exposed silicon nitride is removed, with a silicon nitride insulator strip 20 remaining under first gate electrode G1. Enhanced conduction doped insulators 22 are then formed along each side of first gate electrode G1 and over floating gate electrode 18, as seen more clearly in Fig. 3. The structure is completed by depositing, e.g., a third layer of doped polysilicon and forming therefrom parallel strips A, G2 and B, with strip G2 forming a second gate electrode and strips A and B forming conductors connected to Ndiffusions 14 and 16 through contac...