Browse Prior Art Database

Four Terminal Bipolar Electrically Alterable Read Only Memory

IP.com Disclosure Number: IPCOM000051928D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Bergeron, DL: AUTHOR [+3]

Abstract

An essentially four-terminal bipolar electrically alterable read-only memory is provided which operates with relatively low voltage with the use of graded band gap or silicon-rich insulators. Graded band gap or silicon-rich insulators, or insulators of this type, are disclosed in, e.g., U. S. Patents 3,972,059 and 4,104,675.

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Four Terminal Bipolar Electrically Alterable Read Only Memory

An essentially four-terminal bipolar electrically alterable read-only memory is provided which operates with relatively low voltage with the use of graded band gap or silicon-rich insulators. Graded band gap or silicon-rich insulators, or insulators of this type, are disclosed in, e.g., U. S. Patents 3,972,059 and 4,104,675.

One cell of the memory, illustrated in Fig. 1, is made as a bipolar transistor 10 having an emitter e, base b and collector c, a floating gate 12 insulated from transistor 10 and first and second control gates CG1 and CG2. First control gate CG1 is separated from floating gate 12 by a dual silicon-rich insulator 14 which includes a first silicon-rich region 16, a conventional silicon dioxide region 18 made by chemical vapor deposition and a second silicon-rich region 20. Second control gate CG2 is separated from floating gate 12 by a thin dielectric medium which forms, with gate CG2 and floating gate 12, a capacitor having a high capacitance value.

The cell may be fabricated by forming on a silicon substrate 22 an N+ subcollector layer 24, an N- epitaxial layer 26 and a silicon dioxide layer 28. First and second shallow trenches 30 and 32 are formed in epitaxial layer 26 to the depth of N+ subcollector layer 24 by known techniques, such as by reactive ion etching. Layers of silicon dioxide 34 and 36, about 200 to 400 angstroms thick, are formed on the walls of trenches 30 and 32, and doped polysilicon 38 and 40 is deposited so as to fill trenches 30 and 32, as Illustrated in Fig. 2. The trench 32 may be used to isolate base diffusions of a plurality of NPN transistors 10.

As indicated in Fig. 3, the polysilicon outside of trenches 30 and 32 is etched away and a P- base region 42 and an Nemitter region 44 are formed in epitaxial layer 26 by known techniques, such as ion implantation. The dual silicon-rich insulator 14, indicated in more detail in Fig. 1, is formed on polysilicon 38, which acts as a floating gate, disposed in trench 30. A first metal line for the first control gate CG1 is formed on the dual silicon-rich insulator 14, and a second metal line for the bit line is contacted to the N+ region 44 which forms the emitter e of transistor 10 of Fig. 1. The P- base region 42, which forms...