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Substrate Bias Generator Circuit

IP.com Disclosure Number: IPCOM000051929D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hanafi, HI: AUTHOR

Abstract

This substrate bias generator circuit for FET applications uses a doubl voltage-boosting charge pump circuit in which power consumption is minimized by using clock-driven load devices.

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Substrate Bias Generator Circuit

This substrate bias generator circuit for FET applications uses a doubl voltage-boosting charge pump circuit in which power consumption is minimized by using clock-driven load devices.

The circuit is responsive to a self-starting, free-running oscillator circuit (not shown) which provides the periodic output signal OSC. This signal is inverted by devices T1 and T2 to provide its complement O:SC which drives device T3. Devices T3 and T4 provide a signal on node D that is applied to a Schmitt trigger formed by devices T7, T8, T9 and T10 and capacitor C1. The output of the Schmitt trigger, identified as Phi, is inverted by devices T12 and T13 to provide the signal Phi.

The operation of the substrate bias generator will be described with reference to Figs. 1 and 2.

During the interval between t0 and t1 as shown in Fig. 2, the signals O:SC and Phi are low while O:SC and Phi are high. This condition causes T5 and T15 to conduct, charging capacitors C2 and C3. Capacitor C2 charges to Vdd-Vt5, where Vt5 is the threshold voltage of T5. Capacitor C3 charges to Vdd-Vt5-Vt 17, which equals the voltage on node A minus the voltage on node B, which is established at Vt17. The diode connection of T17, although reducing the charge available on C3, provides some measure of compensation for device threshold voltage variation in the circuits for which the substrate biasing is provided. High threshold voltages will increase the voltage drop across T17...