Browse Prior Art Database

Programmable Arithmetic/Logic Circuit

IP.com Disclosure Number: IPCOM000051930D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

Bechade, RA: AUTHOR [+2]

Abstract

This programmable, minimum delay FET logic circuit forms the basis for 2-bit subunit for providing arithmetic and logic functions. The circuit can be used to provide a ripple carry adder or all 16 2-input logic functions as determined by the state of a number of control lines.

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Programmable Arithmetic/Logic Circuit

This programmable, minimum delay FET logic circuit forms the basis for 2-bit subunit for providing arithmetic and logic functions. The circuit can be used to provide a ripple carry adder or all 16 2-input logic functions as determined by the state of a number of control lines.

Fig. 1 shows the basic circuit which includes a function generating portion (devices 1-10) and a carry generator (devices 11-18). The type of operation performed is determined by the state of control inputs K1 and K2 as follows. K1 K2 Function

0 0 Arithmetic

0 1 Exclusive OR

1 0 Not used

1 1 AND and OR.

An input phase inverter for logic inputs A and B is shown in Fig. 2 and is responsive to input control lines Kin and Kin to enable the independent control of the state, or presence, of each logic input A and B.

An output phase inverter, shown in Fig. 3 enables the state of the function f to be controlled in response to output control lines Kout.

A ripple carry adder can be formed as a 2-bit slice by using two circuits of Fig. 1 coupled together such that the carry out (not) output Cout is applied directly to the carry in terminal Cin of the adjacent stage. The output phase inverters responsive to function generator output f must be controlled so that the output f' of one stage is inverted with respect to the other in order to provide the correct phase for each bit of the binary counter output.

Fig. 4 illustrates how the circuits of Figs. 1, 2 and 3 may b...