Browse Prior Art Database

Compression Buffer

IP.com Disclosure Number: IPCOM000051931D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Gomez, RS: AUTHOR [+2]

Abstract

This article pertains to high speed data buffers used in automatic logi test systems and involves a hardware data compression technique whereby test data is compressed on a per pin basis by storing the test data together with the number of cycles the data is present before different data is required. This technique, when employed, results in the following benefits: - The virtual depth of the buffer would be extended by a significant multiplier over the actual hardware depth. - Fewer actual bits would be needed to store the same amount of data.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Page 1 of 3

Compression Buffer

This article pertains to high speed data buffers used in automatic logi test systems and involves a hardware data compression technique whereby test data is compressed on a per pin basis by storing the test data together with the number of cycles the data is present before different data is required. This technique, when employed, results in the following benefits: - The virtual depth of the buffer would be extended by a

significant multiplier over the actual hardware depth.

- Fewer actual bits would be needed to store the same amount

of data.

The following sequence defines the method of compressing data before entering the data into the buffer 10, as shown by Fig. 1.

1. The first data word is loaded into register 11 from 6 data service (not shown) via lines 12 and 13, and from there it is sent to register 14.

2. A compare, with register 14, is performed by compare circuit 15. The count data of a counter 16 is loaded into the buffer 10 together with the data from register 14 via gate 17, that is, at the same address from address control 18 as the data. This means that if the data does not change for a number of cycles, as is typical in test data, the data compression in depth is equal to the average number of pattern steps without change. Typically this should be greater than 4 or 5 to 1. The data bit compression should be approximately 1/2 the depth compression for the data-counter configuration shown.

3. If a compare is not detected, then the data buffer is loaded with the content of register 14 and the address of the data buffer 10 is incremented. Register 11 is loaded to register 14.

4. If a compare is detected, the counter 15 is incremented and register 11 is loaded to register 14. A compare is made with register 14.

5. To prevent wasted space when either random or repeating patterns dominate, then the sequence of Fig. 2 should be used. Initially the first word from data word source 20 is passed through register 21 to register 22 while the second word will be temporarily stopped in register 21. Once this condition occurs, the compare logic 23 will be enabled, allowing register 22 to be compared against register 21. If there is no compare, register 22 will be loaded into FIELD 25 of the memory, register 21 into FIELD 26 via the multiple...