Browse Prior Art Database

Method to Cause Functional Chips to be Electrically O

IP.com Disclosure Number: IPCOM000051937D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Drotar, JS: AUTHOR [+2]

Abstract

The MC (metallized ceramic) module package must be routinely stress-tested to insure solder joint integrity. This testing which involves thermal cycling of the MC module is commonly called solder fatigue or is electrical resistance. Historically, a solder joint is considered failed or defective once its initial resistance has increased by 200 milli-ohms. Generally, the resistance is measured by a three-point probe technique. A current probe is placed on one substrate pin and a voltage probe is placed on a second with both pins electrically connected to the chip by substrate lines or electrodes. The current and voltage are then measured at a third pin which is connected to the solder joint of interest.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 59% of the total text.

Page 1 of 2

Method to Cause Functional Chips to be Electrically O

The MC (metallized ceramic) module package must be routinely stress- tested to insure solder joint integrity. This testing which involves thermal cycling of the MC module is commonly called solder fatigue or is electrical resistance. Historically, a solder joint is considered failed or defective once its initial resistance has increased by 200 milli-ohms. Generally, the resistance is measured by a three-point probe technique. A current probe is placed on one substrate pin and a voltage probe is placed on a second with both pins electrically connected to the chip by substrate lines or electrodes. The current and voltage are then measured at a third pin which is connected to the solder joint of interest. In this circuit, the current path is from the current probe, through the substrate line, through a solder joint along the aluminum on the shorted chip, through the solder joint being measured and out the IV pin. This method works well for single chip and independently wired multi-chip modules. However, for multi-chip memory modules, where the chips are wired to the substrate pins in parallel, it presents complications.

This situation is shown in the drawing. If both sites are populated with a shorted test chip, then the current has two alternative paths and both solder joints, one on each chip, must fail before an increase in resistance occurs. A simple solution to this problem is to place a shorted chip in one...