Browse Prior Art Database

Variable Threshold Receiver Circuit

IP.com Disclosure Number: IPCOM000051970D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Johnson, RE: AUTHOR [+3]

Abstract

The off-chip receiver circuits (Figs. 1 and 2) are capable of receivin input signal amplitudes of 900 MV (minimum) while maintaining high DC noise immunity. For the input amplitudes shown, a minimum DC noise tolerance of 450 MV is achievable. Nominal delays in the range of 3.5 ns are obtainable to provide good AC noise immunity.

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Variable Threshold Receiver Circuit

The off-chip receiver circuits (Figs. 1 and 2) are capable of receivin input signal amplitudes of 900 MV (minimum) while maintaining high DC noise immunity. For the input amplitudes shown, a minimum DC noise tolerance of 450 MV is achievable. Nominal delays in the range of 3.5 ns are obtainable to provide good AC noise immunity.

For a logical "0" at the circuit input, the feedback current switch voltage threshold (nominal) is: V(T) = R(2) over R(1)+R(2) X V(C) = 1.2 V.

For a logical "1" at the circuit input, the nominal voltage threshold is: V(T) = V(C) - VD1 = .9 V. where VD1 is the voltage across diode D1.

The output of the Fig. 1 circuit is in phase with the input signal and can drive on-chip current switch circuits. The output of the Fig. 2 circuit is also in phase with the input signal and can drive on-chip TTL (transistor-transistor logic) circuits.

Resistor RB limits the input current required at the minimum up level to </- 100 mu a.

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