Browse Prior Art Database

High Performance FET Technology

IP.com Disclosure Number: IPCOM000051972D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for realizing FET devices having thick insulator islands beneath nearly all of the source/drain region in a self-aligned manner. In addition, the thin gate oxide of the FET is self-aligned with respect to source/drain. Parasitic capacitances are substantially reduced by such an arrangement.

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High Performance FET Technology

A method is described for realizing FET devices having thick insulator islands beneath nearly all of the source/drain region in a self-aligned manner. In addition, the thin gate oxide of the FET is self-aligned with respect to source/drain. Parasitic capacitances are substantially reduced by such an arrangement.

The process starts with P/-/ type silicon substrate 2 shown in Fig. 1, and, preferably, through reactive ion etching (RIE), ~ 1 mu m deep trenches are formed in the substrate using photolithography (PL). Then, a layer 4 of about 800 angstroms of thermal SiO(2) is formed. A thick (about 2mu m) layer 6 of N doped (e.g., phosphorus-doped) pyrolytic SiO(2), as shown in Fig. 2, is then deposited. Thereafter, a planarizing coat of photoresist (or polyimide) is applied, and the RIE conditions are adjusted so as to etch back the planarizing coat and SiO(2) layer 6 with practically the same etch rate. In addition, SiO(2) layer 4 (using RIE) is etched in the non-trench regions, the etching being stopped when silicon substrate 2 in the non-trench region is barely exposed, as seen in Fig. 3. Suitable etch-end-point-detect can be used for this purpose.

As shown in Fig. 4, a thin (about 0.5-1.5 mu m) layer of P/-/ type epitaxial silicon 8 is then grown. The silicon is monocrystalline above the exposed silicon of wafer 2. The silicon region 10 above SiO(2) islands 6 is polycrystalline without any adverse consequence, and this region also becomes N/+/ doped as a result of diffusion from the N/+/ doped L SiO(2) of these islands. An extra heat cycle, if essential, (in addition to the heat cycle of the epitaxial growth itself) may be employed to ensure that the entire silicon above the SiO(2) islands is N/+/ doped up to the top surface. The resulting structure at this stage is shown in Fig. 4.

In the next step, a 6-10K angstroms thick pyrolytic SiO(2) layer 12 is deposited, and patterns are formed therein using PL., as shown in Fig. 5. Then, a thin gate thermal oxide 14' (about 500 angstroms) is grown above the exposed P/-/ layer 8 at a relatively low temperature (around 700-850 degrees C), as shown in Fig. 6. At this low temperature, the SiO(2) layer 14 growing simultaneously above exposed N/+/ silicon region 10, as shown in Fig. 6, is about five to six times thicker than the oxide 14' grown above exposed P/-/ layer 8. Using PL, holes are then opened in SiO(2) layer 14 for subsequent metal contacts to N source~drain regions 10. Subsequently, a layer approximately 1 mu m thick of metallization, such as aluminum/copper, is deposited. Using PL, interconnecting patterns in metal layer 16 are formed, and the metal is sintered.

The resulting FET cross-sectional structure at the end of this processing is shown in Fig. 7. A significant feature of this structure is that thick SiO(2) insulator islands are formed beneat...