Browse Prior Art Database

Multi Function Latch

IP.com Disclosure Number: IPCOM000051977D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+3]

Abstract

Conventional PLA latch schemes involve multiple mask changes using additional area. By using fixed true-complement circuits and an AOI circuit as a buffer between two OR array outputs (alpha and beta) and a polarity hold latch input (Fig. 1), 96 or more logic functions can be generated by first level metal personalization. This latch scheme brings out one extra logic level which allows more flexible PLA design at no cost in silicon area. Fig. 1A depicts the conventional PLA design. Fig. 1B depicts the PLA design in accordance with the disclosed technique.

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Multi Function Latch

Conventional PLA latch schemes involve multiple mask changes using additional area. By using fixed true-complement circuits and an AOI circuit as a buffer between two OR array outputs (alpha and beta) and a polarity hold latch input (Fig. 1), 96 or more logic functions can be generated by first level metal personalization. This latch scheme brings out one extra logic level which allows more flexible PLA design at no cost in silicon area. Fig. 1A depicts the conventional PLA design. Fig. 1B depicts the PLA design in accordance with the disclosed technique.

First level metal personalization simplifies process steps. Product build time is decreased. Having only one basic buffer circuit to personalize simplifies fabrication. In the illustrated example (Fig. 2), the buffer circuits are an Exclusive OR circuit including a true/ complement circuit and an AND-OR-Invert circuit.

Fig. 2 shows a true/complement circuit and an AOI circuit connected between an OR array and polarity hold latch 1. As an example, the Exclusive OR circuit is shown with dotted lines connected between the two true/complement circuits and AOI (AND-OR-Inverter) circuit.

For given inputs a and 9 the true/complement circuit generates

and beta, beta ##. The exclusive OR output (alpha beta alpha be to the polarity hold latch input (data point). Polarity hold latch 1 and polarity hold latch 2 are provided to comply with level sensitive scan design (LSSD) rules. The LSSD rules are set...