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Selectable Up Level, Off Chip Driver Circuit

IP.com Disclosure Number: IPCOM000051979D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Boudon, GM: AUTHOR [+3]

Abstract

This driver circuit accepts input logic signal levels of 0.3 V to 1.7 V and provides output logic signal levels of 0.5 V at 16 milliamperes and either 1.6 V or 2.4 V at 400 microamperes with a VCC supply of 3.4 V. Output F is a logical NAND of inputs A, B and C.

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Selectable Up Level, Off Chip Driver Circuit

This driver circuit accepts input logic signal levels of 0.3 V to 1.7 V and provides output logic signal levels of 0.5 V at 16 milliamperes and either 1.6 V or
2.4 V at 400 microamperes with a VCC supply of 3.4 V. Output F is a logical NAND of inputs A, B and C.

An UP level at A, B and C causes T1 to turn ON through R1 and R2. T6 turns ON through R8 and maintains a DOWN level at F. The collector through R5 causes T2 to conduct, pulling its collector DOWN through R3. This holds T3 OFF.

A DOWN level at A, B or C turns T1, T2 and T6 OFF. T4 and T5 then turn ON through R2, pulling output F UP to 1.6 V. Simultaneously, if control input X is tied to VCC, T3 also turns ON through R3. This will result in pulling output F UP to 2.4 V. Correspondingly, if control input X is tied to ground, T3 is held OFF and output F remains at 1.6 V.

R6, R7 and R9 assist T2, T5 and T6 in turning OFF by providing a discharge path for base charge. R5 prevents T2 from hogging current from T1 and T6. In order to reduce external network ringing, R8 is included to limit the output falling transition rate. R4 limits transient di/dt as well as limiting the maximum UP-level output current.

D1 permits all drivers in a bank to be connected to one control line for off-chip control. D5, D6 and D7 prevent saturation of T1, T2 and T6. D2, D3 and D4 facilitate the logic NAND function.

By connecting all drivers in a bank to a common control line X, the minimum ...