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Enhanced Performance "AND" ROM

IP.com Disclosure Number: IPCOM000052002D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Zbrozek, JD: AUTHOR

Abstract

In an FET read-only storage of the series string or "AND array" type, i which programming is accomplished through selective enhancement/depletion implantation, improved interrogation speed is realized when the FETs which serve as memory cells are implanted so that the enhancement-mode devices have a threshold of zero volts and the depletion devices are additionally shifted negatively. Sensing is accomplished by a race to drive a latch against a reference waveform having a time constant nominally half of that of the string when the interrogated FET is a depletion-mode FET.

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Enhanced Performance "AND" ROM

In an FET read-only storage of the series string or "AND array" type, i which programming is accomplished through selective enhancement/depletion implantation, improved interrogation speed is realized when the FETs which serve as memory cells are implanted so that the enhancement-mode devices have a threshold of zero volts and the depletion devices are additionally shifted negatively. Sensing is accomplished by a race to drive a latch against a reference waveform having a time constant nominally half of that of the string when the interrogated FET is a depletion-mode FET.

The drawing shows the store, sometimes called an AND array, in which a bit of information is permanently built into each transistor by its being made either as a depletion-mode FET or an enhancement-mode FET. The strings comprise memory FETs 1, a typical number in a string being eight, and an X select FET 3, which is not a memory transistor. Each string connects to one sense line 7, each having a Y select transistor 9. The drawing shows in detail only three memory strings connected to the outer sense line, but typically, as suggested in the drawing identical strings will exist throughout three dimensions of the memory. +The X select lines 11 extend through the memory in parallel. The eight Z select lines 13 each wind through all the corresponding FETs in the memory.

Absent implanting, the threshold of all devices on a chip typically would be about zero volts. In conventional manufacture, the entire chip is implanted to boost all thresholds about one volt, in a step known as the channel tailor implant. Devices are additionally subject to a selective implant to depletion type, based on the required data pattern.

In such a system, enhancement-...