Browse Prior Art Database

Paged Read Only Storage

IP.com Disclosure Number: IPCOM000052003D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Zbrozek, JD: AUTHOR

Abstract

In an FET read-only store of the series string or "AND array" type, one of the axes of decode required to interrogate the array is formed by connecting together the gates of like positioned transistors in each of many series strings within the array. The result of this connection is a set of networks exhibiting large capacitive loadings, and which are difficult to drive quickly with small economical circuits. It is herein proposed that the address bits associated with this particular, heavily loaded axis of decode be grouped together and considered as high-order or "page-select" bits, such that these address bits are allowed to change only on dedicated "page-select" cycles.

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Paged Read Only Storage

In an FET read-only store of the series string or "AND array" type, one of the axes of decode required to interrogate the array is formed by connecting together the gates of like positioned transistors in each of many series strings within the array. The result of this connection is a set of networks exhibiting large capacitive loadings, and which are difficult to drive quickly with small economical circuits. It is herein proposed that the address bits associated with this particular, heavily loaded axis of decode be grouped together and considered as high-order or "page-select" bits, such that these address bits are allowed to change only on dedicated "page-select" cycles.

As no output could be expected from the memory on such a cycle, memory throughput would suffer a large degradation unless excessive page hopping was avoided. However, the following benefits and opportunities would result:

1. The time available for charging and discharging the heavily loaded decode networks would increase from a small fraction of a cycle to a full cycle, allowing approximately a tenfold reduction in the size and power of the required drivers.

2. Address buffers and decoders already in place to serve another axis of decode may be time-multiplexed into a second service, processing page-select address. In this way, the silicon area required to support several buffer and decoder circuits, as well as several I/O pads, may be saved.

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