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Random Access Memory Implementation of a Beamformer

IP.com Disclosure Number: IPCOM000052012D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 6 page(s) / 177K

Publishing Venue

IBM

Related People

Terrill, WA: AUTHOR [+3]

Abstract

In the reception of radiated wave information in a medium, such as long wave acoustical waves in water, it has been found useful to employ a phased array of sensors to detect the direction of emanation of the source of the acoustical waves. Disclosed herein is an improved technique for detecting the direction of emanation of acoustical waves, commonly known as beamforming.

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Random Access Memory Implementation of a Beamformer

In the reception of radiated wave information in a medium, such as long wave acoustical waves in water, it has been found useful to employ a phased array of sensors to detect the direction of emanation of the source of the acoustical waves. Disclosed herein is an improved technique for detecting the direction of emanation of acoustical waves, commonly known as beamforming.

The beamformer receives 960 elements in a processing cycle, and outputs 600 fullbeams over ten depression/elevation (D/E) angles to signal-processing functions. Additionally, 2400 quarterbeams are required for use in subsequent tracking functions. Therefore, the basic beamformer module forms quarterbeams. Subsequent halfbeam and fullbeam generation is accomplished by straightforward adder circuits and will not be discussed in this article.

The beamformer is designed to develop the aperture pattern shown in 1. The fullbeam aperture consists of 20 staves horizontally by 16 rings vertically. A unique aperture pattern is provided to form each of 10 D/E angles. The beamformer architecture can be modified to accommodate any number of ring/stave/DE combinations.

The chosen architecture forms quarterbeams by the addition of eight bits (1 bit per ring) per stave, with 10 staves accumulated serially.

Two quarterbeams are formed (top-left and top-right for a top quarter- beamformer) in each quarter-beamformer for each of 10 D/E angles. Since 10 D/E angles are generated, a total of 20 quarterbeams are generated from each quarter-beamformer in a processing cycle.

The quarter-beamformer, shown in Fig. 2, receives serial element data in a 16-ring parallel by 60-beam serial format, each data input being one bit. The output data format is eight-bit quarterbeam data (top and bottom) for each beam, generating 120 parallel quarterbeams by 20 serial guarterbeams (2400 quarterbeams total) per cycle.

The quarter-beamformer described herein utilizes a unique random-access memory (RAM) architecture to efficiently implement element storage requirements and enables a simple address generator to control the beam formation.

The architecture, shown in Fig. 3, consists of 16-6Q bit shift registers (SHF REG), 16 1K x 60 RAMs and 120 quarter-beamformers (Q-BMFR).

The SHF REG is used to initially receive element data from the front end, and to circulate the data in conjunction with the RAM architecture requirements.

The RAMs store 48 time samples of element data in an architecture which supports a simplified addressing technique.

The Q-BMFRs read and accumulate quarterbeam data, and align data sent to the tracker selection logic and half-beamformers.

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To describe the RAM architecture, one of 16 SHF REG/RAM modules, shown in Fig. 4, will be examined in detail.

The 1K x 60 RAM is divided vertically into 20 circular buffers, each circular buffer being 48 addresses deep. Each circular buffer stores 48 time samples of a given element. T...