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Browse Prior Art Database

Non Latching Short Circuit Protect for I/O Drivers

IP.com Disclosure Number: IPCOM000052020D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Beers, HR: AUTHOR

Abstract

Most short-circuit protect schemes for I/O interface drivers involve some mechanism (temperature, voltage or current) that senses a shorted interface and through various mechanisms (shift register latch, thermal cut-off, etc.) hold the output of the driver off until some digital command resets the circuit after the short has been removed or in the case of temperature sensing, the module cools off. The drawing shows a circuit for protecting the driver output while shorted without latching in the protected state. Added features of this circuit are that it is active only during the low level input state (high output) and insensitive to any input transitions. Circuit Description.

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Non Latching Short Circuit Protect for I/O Drivers

Most short-circuit protect schemes for I/O interface drivers involve some mechanism (temperature, voltage or current) that senses a shorted interface and through various mechanisms (shift register latch, thermal cut-off, etc.) hold the output of the driver off until some digital command resets the circuit after the short has been removed or in the case of temperature sensing, the module cools off. The drawing shows a circuit for protecting the driver output while shorted without latching in the protected state. Added features of this circuit are that it is active only during the low level input state (high output) and insensitive to any input transitions. Circuit Description.

Resistors R1 and R2 are ratioed such as to insure that transistor T2 conducts before T3, thereby insuring that T6 is off for rising and up-level inputs.

R3 and R5 are ratioed such as to adjust the collector voltage of T5, thus setting the turn-on voltage of T6 which determines the voltage at which the protect circuit activates.

Assume a high level output. T1, T2 and T3 are off due to a low input voltage. T5 is conducting, presenting a base voltage to T6 of approx. 3 volts. If the output is pulled low, at h3 V - 2 VBE's, T6 will conduct, pulling the base of T7 low. Thus, T8 turns off, preventing damage to T8 from the externally applied short.

When there is no longer a forced low on the output, T6 will release its hold on T7, and if the input...