Browse Prior Art Database

Error Checking of ECC Generation Circuitry

IP.com Disclosure Number: IPCOM000052022D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

This scheme permits error checking of the circuitry generating error correcting code (ECC) check bits.

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Error Checking of ECC Generation Circuitry

This scheme permits error checking of the circuitry generating error correcting code (ECC) check bits.

In a (144,128) ECC code where a code word is processed 2 bytes at a time with ECC check bits generated and accumulated in each time frame, a physical failure in the ECC generation logic 10 can cause multiple bit errors.

When every column of the ECC parity check matrix has an odd number of 1's, the circuitry inside the dotted lines 12 of the diagram represents the additional hardware for the checker.

All single bit errors in an ECC code word are detectable by the checker. Multiple bit errors in a code word are detectable with a 99.6% accuracy.

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