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Error Checking Technique for Error Correction Logic

IP.com Disclosure Number: IPCOM000052023D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR [+2]

Abstract

This error checking technique can be used to detect errors caused by th hardware failures of an error correction system suing an error correcting code (ECC).

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Error Checking Technique for Error Correction Logic

This error checking technique can be used to detect errors caused by th hardware failures of an error correction system suing an error correcting code (ECC).

The error correction hardware of an ECC is subject to failures.

For example, the decoder for erroneous bit positions may turn on incorrect bits. As a result, the output ECC word after correction may become an improper code word. The improper code word can be detected by checking if the syndrome of the code word is nonzero. This requires a separate syndrome generator.

For a multiple error correction system, a separate syndrome generator to recheck an ECC code word is expensive. For example, consider the (144,128) code whose parity check matrix H is shown in Fig. 1. A syndrome generator calculates the 16 exclusive OR equations represented by the 16 row vectors of
H.

The error positions of an error correction system are in encoded form before they are decoded. For the (144,128) code the error positions are represented by 8-bit patterns before the decoding. These 8-bit patterns are the column vectors of the matrix M shown in Fig. 2. By nature, the column vectors are distinct. In addition, a proper code word satisfies the 8 equations represented by the row vectors of M.

If the 8 equations are used to check the validity of a code word, then all single bit and double bit errors in the code word are detectable. An additional equation that checks the overall parity...