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Programmable Frequency Divider

IP.com Disclosure Number: IPCOM000052025D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

A conventional digital frequency divider 10 makes use of a binary flip11 for dividing by 2 and a plurality of flip-flops 12-14 arranged as a counter for dividing by a binary number "n" where n is proportional to the number of counter stages. Fig. 1 shows the timing relationship of input to output signals. It should be noted that the divide by 2 output is available sooner than the divide by 4 output, which is available sooner than the divide by 8 output, etc. This variation in counter pulse output has the same effect as a counter with variable delay. Fig. 2 shows a frequency divider 20 which overcomes this problem by preconditioning the counter 10' so that the first input pulse causes all the output signals to become active with a constant delay regardless of the selected output.

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Programmable Frequency Divider

A conventional digital frequency divider 10 makes use of a binary flip11 for dividing by 2 and a plurality of flip-flops 12-14 arranged as a counter for dividing by a binary number "n" where n is proportional to the number of counter stages. Fig. 1 shows the timing relationship of input to output signals. It should be noted that the divide by 2 output is available sooner than the divide by 4 output, which is available sooner than the divide by 8 output, etc. This variation in counter pulse output has the same effect as a counter with variable delay. Fig. 2 shows a frequency divider 20 which overcomes this problem by preconditioning the counter 10' so that the first input pulse causes all the output signals to become active with a constant delay regardless of the selected output. By the addition of a multiplexer 22 for output selection and a shift register 24 for dynamic frequency selection this mechanism behaves as a dynamically controlled digital pulse divider with relatively constant delay. The limits of frequency division are a function of the number of stages in the synchronous counter.

Divider 20 operates as follows. The frequency required is obtained by loading a bit pattern into the shift register (8R) 26. This pattern enables the corresponding multiplexer 22 input and prepares counter 10' for preconditioning via the AND, OR, INVERT circuits. A counter preset pulse loads the required pattern into counter 10'. The next frequen...