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Browse Prior Art Database

Electronic Interface with Variable Erase Delay for Magnetic Disk Machine

IP.com Disclosure Number: IPCOM000052030D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 99K

Publishing Venue

IBM

Related People

Jahnke, RC: AUTHOR [+4]

Abstract

This machine utilizes a jacket-flexible magnetic disk assembly of the type disclosed in U. S. Patent 3,668,658 and a disk retaining, accessing and transducing mechanism substantially as shown in the IBM Technical Disclosure Bulletin 23, 2447-2450 (November 1980).

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Electronic Interface with Variable Erase Delay for Magnetic Disk Machine

This machine utilizes a jacket-flexible magnetic disk assembly of the type disclosed in U. S. Patent 3,668,658 and a disk retaining, accessing and transducing mechanism substantially as shown in the IBM Technical Disclosure Bulletin 23, 2447-2450 (November 1980).

Referring to Fig. 1 showing the interface, read/write windings 120 and 122, respectively, in read/write heads are connected to head select matrix 124, and the tunnel erase windings 126 and 128, respectively, in the read/write heads are connected to tunnel erase driver 130. Various combinations of control bits are successively supplied to ACCESS 0 and ACCESS 1 lines 132 and 134, respectively, and thereby to access driver circuitry 136 in order to cause stepper motor 100 to move the carriage to the desired position and the read/write heads to the desired concentric tracks in their respective groups of tracks on the disk.

A high or low WRITE GATE signal on WRITE GATE line 148 is effective to put the interface shown in Fig. 1 in either WRITE MODE or READ MODE. In WRITE MODE, a succession of bits is supplied to WRITE DATA line 138, and these bits are supplied through write driver 146 to matrix 124 so that either of the windings 120 or 122 is effective for writing information on the disk corresponding to the signal supplied on the WRITE DATA line. In the writing action, write driver 146 toggles back and forth with the high and low bits of write data on line 138 to thus write these bits on the disk. The WRITE GATE signal is supplied to driver 130 (through delay circuitry 150) so that the tunnel erase windings 126 and 128 are effective in WRITE MODE but not in READ MODE. In either WRITE MODE or READ MODE, one or the other of the heads activated by windings 120 or 122 is selected by applying a high or low HEAD SELECT signal on HEAD SELECT line 142.

The HEAD SELECT line is effective on matrix 124 so as to cause either the winding 120 or the winding 122 to be effective in WRITE MODE or READ MODE, and the HEAD SELECT signal on line 142 applied to driver 130 is effective to cause either the erase winding 126 or the erase winding 128 to be effective in WRITE MODE.

In WRITE MODE, the HEAD SELECT signal on line 142 is effective on DC current source 144 so that different DC currents are supplied to write driver 146 from source 144 depending on which head and therefore which group of tracks are being written. There is a greater DC current thus supplied from source 144 to write driver 146 for the outer band of tracks, and this current is supplied through head select matrix 124 to read/write winding 120 for head 30. When the signal on HEAD SELECT line 142 is effective for selecting the inner head, current source 144 supplies a smaller DC current to write driver and winding 120 through head select matrix 124.

An inactive condition of the WRITE GATE signal on line 148 makes pre- amplifier 152, filters 154 and detector 156...