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Task Assignment for Multiple Microprocessor System

IP.com Disclosure Number: IPCOM000052033D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Corso, JA: AUTHOR [+4]

Abstract

Self-identified multiple microprocessors 1, 2 access common memory 3 to execute tasks in partitions 31 as specified by stored control blocks 32 and configuration-table entries 33.

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Task Assignment for Multiple Microprocessor System

Self-identified multiple microprocessors 1, 2 access common memory 3 to execute tasks in partitions 31 as specified by stored control blocks 32 and configuration-table entries 33.

Microprocessors 1, 2 include external-register busses 11-14 and 21-24 for interfacing I/O devices. Some of these lines are hard-wired to supply voltages, as at 14 and 24, to form a unique code for each processor. Thus, each processor can identify itself by reading a particular register. Memory 3 grants cycles to processors 1, 2 on a rotating-priority basis, using address, data and control busses A, D, C. Processors 1, 2 have an atomistic lock instruction RXW which reads a byte from memory, exclusive -OR's it with a processor-register mask byte, retains the original data value, and copies the result back to memory before releasing memory 3 to any other processor.

Tasks contained in individual partitions 31 are specified by four-byte control blocks 32 at fixed addresses. Each block contains various flags, the beginning address of a particular partition, and lock bits indicating which processors are allowed to access that partition. Before a processor enters a partition, it will RXW that partition's lock bits with its unique identity code. If an analysis of the result shows that no other processor had already claimed that partition, the processor proceeds to execute commands from the partition, ultimately releasing it with another RXW to t...