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Apparatus Supporting Half Duplexed Encoding/Decoding Action

IP.com Disclosure Number: IPCOM000052053D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 97K

Publishing Venue

IBM

Related People

Langdon, GG: AUTHOR

Abstract

This invention relates to common apparatus supporting the half-duplexed arithmetic string encoding and decoding action. Such an apparatus is premised on the observation that adding a trial augend to a dedicated arithmetic unit input register during an add and shift encoding cycle utilizes the same data path as adding the complement (subtraction) of a trial augend to the same register during the subtract shift decoding cycle.

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Apparatus Supporting Half Duplexed Encoding/Decoding Action

This invention relates to common apparatus supporting the half-duplexed arithmetic string encoding and decoding action. Such an apparatus is premised on the observation that adding a trial augend to a dedicated arithmetic unit input register during an add and shift encoding cycle utilizes the same data path as adding the complement (subtraction) of a trial augend to the same register during the subtract shift decoding cycle.

Conceptually, the encoder is a finite state machine whose state in this embodiment is a 16-bit number T. The encoder also contains the 16-bit "working end" of an arithmetic code string in register C. Encoding action involves ascertaining whether the symbol to be encoded is the less probable symbol (LPS) or the more probable symbol (MPS) and the skew number k. The encoder forms a trial augend (TA) according to the relation TA = T (1 - 2/-k/).

If an input symbol value LPS occurs, the encoder adds TA to the working end of the code string in order to form the new word string. The encoder left shifts out k bits from the working end of the code string and similarly shifts register C using "0 fill". The internal state T of the encoder remains unchanged. If the bit to be encoded is MPS, then the coder does not add TA to the working end of the code string. Rather, it tests for normalization. That is, if the leftmost bit is "1", then TA is already "normalized" and T is assigned the value TA. However, if the leftmost bit of TA is "0", then bit C(0) is outputted. At this point, TA is left shifted one bit and assigned to T. Concurrently, C is then left shifted one bit. This decoding action is depicted in both flow diagram and data flow formats in Fig. 1.

The decoder needs only to subtract shift. The decoder contains the most significant bits of the code string in register C. It also is possessed of an internal state T. Knowing the skew k, the...