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High Capacity Controlled Access System

IP.com Disclosure Number: IPCOM000052060D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Powell, KE: AUTHOR

Abstract

This access system enables a single central processing unit to handle a multiple of card-actuated terminals. Multiplexer hardware components are arranged as communications controlling circuitry.

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High Capacity Controlled Access System

This access system enables a single central processing unit to handle a multiple of card-actuated terminals. Multiplexer hardware components are arranged as communications controlling circuitry.

Data separation and multiplexing are accomplished with hardware, and a single processor is supplied with data from the separator/multiplexer. The separator/multiplexer replaces the interface hardware normally utilized with a card accessed system, and cost and physical size are approximately the same. The processor is relieved of the task of data separation and is not interrupted until each card actuation or terminal transaction has been verified. In this manner, CPU throughput is increased, while the software requirements are reduced.

A clock and associated control circuit 20 provides a four-bit address over a parallel conductor bus to control the input multiplexer which samples the data input (DI) lines from card-actuated terminals 1-16. When a terminal is activated by a card, the output of the multiplexer changes state and this signal is applied to the clock-control circuit 20. This stops the multiplexer clock and provides a data path from the terminal to a data separator 24. The separator 24 converts the F/2F reader signal to B:CD and stores the data in a buffer.

When this is complete, the data separator 24 signals the CPU over the data ready P1 line. The multiplexer clock control circuit 20 delivers four-bit numerical addresses over a four-wire bus to the three multiplexer c...