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Silicon Gate MOSFET with Self Aligned Buried Source and Drain Contacts

IP.com Disclosure Number: IPCOM000052088D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 126K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR

Abstract

This article relates generally to a process for fabricating semiconductor devices and more specifically to a process for fabricating a silicon-gate MOSFET with self-aligned source and drain contacts.

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Silicon Gate MOSFET with Self Aligned Buried Source and Drain Contacts

This article relates generally to a process for fabricating semiconductor devices and more specifically to a process for fabricating a silicon-gate MOSFET with self-aligned source and drain contacts.

Referring now to Fig. 1, there is shown a p conductivity-type substrate 1 containing a pair of fully recessed oxide regions 2. A gate region 3 is shown delineated in an npolysilicon layer 4 and in an overlying layer 5 of silicon dioxide. The structure of Fig. 1 is obtained by masking and etching layer 5 and preferentially etching n+ polysilicon layer 4. Layers 4 and 5 had been previously deposited on substrate 1 in which recessed oxide regions had been formed by well known techniques. In Fig. 1 exposed portion 6 of substrate 1 will become the gate region of the ultimate device.

Fig. 2 shows the resulting structure after a thin gate oxide 7 is thermally grown on exposed surface 6 after a layer 8 of silicon dioxide is formed by chemical vapor deposition and after an annealing step has been carried out to form nconductivity-type junctions 9 from portions of layer 4 which extend beyond recessed oxide regions 2.

Fig. 3 shows the resulting structure after thin oxide 7 has been removed using a reactive ion etch in the usual way.

The structure of Fig. 4 results after the following steps: Gate oxide 7 is regrown by a thermal oxidation step. An n+ conductivity-type polysilicon layer 10 and a silicon dioxide layer 11 are deposited in successive steps. A photoresist layer 12 is then spun on the surface to provide a surface which is relatively planar..

Fig. 5 shows the resulting structure after a step of blanket reactive ion etching of photoresist layer 12. Etching stops when portions of resist layer 12 are removed everywhere except over gate region. As can be seen from Fig. 5, portions of SiO(2)layer 11 are now exposed.

Using resist 12 as a mask, the exposed portions of SiO(2)layer 11 are etched. The remainder of resist layer 12 is now removed and the thus exposed portions of npolysilicon layer 10 are etched leaving behind, as shown in Fig. 6, an npolysilicon region 13 which is disposed in insulated spaced relationship from surface 6 by thin oxide layer 7, forming the gate electrode for the ultimate device. A layer 14 of SiO(2) is then deposited by chemical vapor deposition.

Fig. 7 shows the resulting silicon-gate MOSFET with self-aligned buried source and drain contacts. The final device is achieved by opening contact holes in layer 14 such that metallization 15 contacts portions of npolysilicon layer 4, the end portions of which are in contact with junction regions 9. Although not shown...