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Browse Prior Art Database

Module Construction For Very High Volume Packaging Density

IP.com Disclosure Number: IPCOM000052090D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 153K

Publishing Venue

IBM

Related People

Tsui, F: AUTHOR

Abstract

This article relates to the structure of a module which permits a very high volume-packaging density to be achieved. The resulting module is applicable to Josephson circuitry as well as semiconductor and other technologies.

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Module Construction For Very High Volume Packaging Density

This article relates to the structure of a module which permits a very high volume-packaging density to be achieved. The resulting module is applicable to Josephson circuitry as well as semiconductor and other technologies.

The module of this article can be constructed as follows: Referring now to Fig. 1, shown therein is an integrated-circuit chip 1 having a plurality of slots 2 cut in a pair of opposing parallel edges of chip 1. Slots 2 can have a length up to 1/3 of the dimension of chip 1 in the cutting direction. A plurality of fillets 3 are shown disposed about the periphery of slots 2 and on the two vertical parallel edges of chip 1.

Fig. 2 is a blow-up of a portion of Fig. 1 showing fillets 3 and their associated wiring interconnections 4. Further wiring interconnections may be disposed any place on chip 1 in addition to circuitry in the form of active and passive devices. A plurality of chips 1 are utilized to make up the final structure of the module.

An additional chip 5 containing wiring, slots 2 and fillets 3 is used as a pedestal chip from which a plurality of pins protrude by which electrical connection can be made to a circuit board which holds a plurality of modules. Fig. 3 shows such a pedestal chip 5, in which slots 2 similar to those shown in Fig. 1 have been cut. Fillets 3 are shown disposed along the vertical edges of pedestal chip 5 and around the periphery of slots 2. In addition, a plurality of pins 6 extend from the surface of pedestal chip 5 to form module pins which will later allow electrical connections to be made between the pedestal chip and a board.

Figs. 4 and 5 show the relationship between pins 6, wiring 4 and fillets 3, with plated-through holes and without plated-through holes, respectively. In Fig. 4, fillets 3 and wiring 4 are disposed on both sides of pedestal chip 5, and plated- through holes 7, filled with conductive material, are connected to pins 6 via pads 8 disposed on the surface of pedestal chip 5. Fig. 5 has fillets 3, wiring 4, pins 6 and pads 8 disposed on only one side of pedestal chip 5. Depending on the application, either of the options shown in Figs. 4 and 5 may be utilized.

As shown in Fig. 6, a plurality of chips 1 and a pedestal chip 5 are arranged in a stack and joined together by two side pieces 9 to form a module. Chips 1 and pedestal chip 5 are held in fixed relation to side pieces 9 by means of soldered L-joints 10, which, as shown in Fig. 7, interconnect fillets on chips 1 or pedestal chip 5 with those on the surface of side pieces 9. Fillets 3, disposed on the surface of side pieces 9, are interconnected by wiring, in a similar way as wiring 4 shown in Fig. 2, to provide interconnections among the chips 1 and pedestal chip 5, as needed.

Also shown in Fig. 6, in addition to the side pieces 9, wiring strips 11, each provided with fillets 3 and wiring 4 interconnecting the fillets 3, are inserted into slots 2...