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Row Column Bypass Mechanism For An Array Of Processing Elements

IP.com Disclosure Number: IPCOM000052092D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

Hong, SJ: AUTHOR [+2]

Abstract

A large array of processing elements may encounter serious reliability and availability problems. The following scheme helps to improve both these measures, thereby rendering an array system practical.

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Row Column Bypass Mechanism For An Array Of Processing Elements

A large array of processing elements may encounter serious reliability and availability problems. The following scheme helps to improve both these measures, thereby rendering an array system practical.

The basic idea involves bypass of a defective element in the array of processing elements. The bypass is accomplished by deselecting the row and column associated with the affected element and by routing signals from the neighbors of the deselected row/column across the row/column. (It is assumed that the defective cell has been identified by some diagnostic procedure before the reconfiguration takes place.) The additional circuitry required to accomplish this is shown in Figs. 1 through 3. The hard-core portion introduced by this scheme is small compared to the circuitry in the original processing element, and hence assumed to remain functional even when the processing element is defective.

The additional circuitry on the element 2 is shown in Fig. 1. When the row/column bypass signal 4 is '1', the 1 out of 2 selectors select the bypassed signal 6. When the bypass signal is '0', the original element output set 8 is selected out at 10 to the neighboring elements.

Fig. 2 shows the global bypass signal application. To bypass rows +12 and 14 or columns 16 and 18, the supervisor sets the bypass latch values for these rows and columns to 1. The setting of these latches, 20 and 22 for rows 12 and 14 respectively, and 24 and 26 for columns 16 and 18 respectively, can be accomplished in a variety of manners, one of which is to connect all the latches in a shift register chain and serially scan in the bypass bits.

When a row (or column) is bypassed, the supervisor selector lines must be shifted over such that the reconfigured array is transparent to the array indexing mechanism of the supervisor. This can be accomplished by the hardware remapping of the supervisor row/column selector lines, as shown in Fig. 3. In this figure, a maximum of two bypasses in one direction is assumed. A straightforward extension of the circuit shown in Fig. 3 can be made for an arbitrary number of ma...