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Direct Coupled AC Powered Latch

IP.com Disclosure Number: IPCOM000052102D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Gheewala, TR: AUTHOR [+2]

Abstract

This article relates generally to Direct Coupled Logic (DCL). More specifically, it relates to a high density AC powered data latch with SCAN and LSSD (Level Sensitive Signal Detection). In DCL, isolation between the gate and control currents is provided by a Josephson junction which switches into the non-zero voltage state. This eliminates the need for electromagnetically isolated control lines as in the three-junction interferometer, and results in a factor of 2-3 improvement in circuit density.

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Direct Coupled AC Powered Latch

This article relates generally to Direct Coupled Logic (DCL). More specifically, it relates to a high density AC powered data latch with SCAN and LSSD (Level Sensitive Signal Detection). In DCL, isolation between the gate and control currents is provided by a Josephson junction which switches into the non- zero voltage state. This eliminates the need for electromagnetically isolated control lines as in the three-junction interferometer, and results in a factor of 2-3 improvement in circuit density.

The figure shows a schematic for the proposed AC powered DCL latch 1. G1 and G2 are DCL two-input AND gates 1 with DOT-ORs at each input.

Incoming DATA may be stored in the superconducting storage loop 2 consisting of a three-junction interferometer Q1 and crossing inductance L, with the help of ACN (Activation Combinatoric Network).

Data is stored when the applied AC power goes down. A "1" is stored in loop 2 as a circulating current of either polarity corresponding to a certain number of flux quanta, whereas a "0" is the absence of a circulating current. Device J1 is a protective Josephson junction which improves the noise immunity of G2. The self-gating AND (SGA)
[2], which also has the same power supply as G1 and G2, senses the state of the latch at the beginning of the cycle and provides true
(T) and complement (C) outputs.

As shown in the figure, the SET, SCAN and LSSD functions may be incorporated into the DCL latch.

The above-des...