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Computer Timing Verifier

IP.com Disclosure Number: IPCOM000052103D
Original Publication Date: 1981-Apr-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Frisiani, AL: AUTHOR [+2]

Abstract

A vital requirement for an LSI or VLSI computer is that its timing constraints not be violated. The timing constraints are expressed by means of clock times associated with various registers; the violations are effected by too long delays between these registers. Straightforward implementations of timing verifiers require excessively frequent access to secondary storage, which exacerbates running time.

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Computer Timing Verifier

A vital requirement for an LSI or VLSI computer is that its timing constraints not be violated. The timing constraints are expressed by means of clock times associated with various registers; the violations are effected by too long delays between these registers. Straightforward implementations of timing verifiers require excessively frequent access to secondary storage, which exacerbates running time.

The technique described here substantially improves on speed of computation as a result of two notions, the "T-unit" concept and the "x-notation", plus a special parallel processor for performing the computation.

A T-unit is a subset of the entire design, selected dynamically by the maximum number of primary inputs or inputs from chips already chosen to be T- units. For a given T-unit, some of its delay inputs are known from initial considerations and previous computations; others will be unknown and assigned the value x. If the delay of one of the inputs of a circuit is unknown, i.e., has value x, then its output also has value x. A T-unit may consist of several chips.

It is assumed that the delay values of primary inputs are known (supplied by the designer). If the delays of the inputs to a circuit are known, then the delay of its output is the maximum of its input delays, plus the intrinsic delay of the circuit itself, this latter being previously computed from the physical design. If a critical time is associated with a given register, then the critical chains causing them is computed via a back-up process.

Repetitions of these calculations are performed until the accumulated delay at each circuit (removing the x's) is known, the number of repetitions being bounded by the technology, a typical value being 4 repetitions an LSSD (level sensitive scan design) design is assu...