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Testing Enhancements for TDI Arrays

IP.com Disclosure Number: IPCOM000052122D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR [+2]

Abstract

Time displayed information (TDI) arrays can have their testing enhanced by providing an input register with a voltage-controlled input and a transfer gate in place of the normal fat 0 input found on such arrays.

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Testing Enhancements for TDI Arrays

Time displayed information (TDI) arrays can have their testing enhanced by providing an input register with a voltage-controlled input and a transfer gate in place of the normal fat 0 input found on such arrays.

By utilizing an input register whose signal content is controlled by the voltage- controlled input circuit, a known signal, for example, a fat 0, is placed in all of the TDI arrays. This results in two important advantages. First, the dark signal non- uniformity of the scanner is reduced, one component of the dark signal being the difference in the fat 0 caused by photo tolerances, oxide thickness variation, profile differences, etc. In this instance, by generating the fat 0 from one source, improved fat 0 matching is achieved. The second advantage is realized by introducing a known signal pattern via the voltage-controlled input and monitoring the output.

In this way the functionality of all the CCDs (charge-coupled devices) and transfer circuits may be checked and faults, such as faulty transfer gates, missing or additional oxide isolation, open lines, poor transfer efficiency, poor overlap, etc., can be detected.

Thus, the invention provides a method of electrical test at a wafer level that does not require expensive, difficult illumination and allows a pattern sensitivity test of the array without imaging a moving pattern on the device.

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