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High Capacitance RAM Cell using Two Layers of Polysilicon

IP.com Disclosure Number: IPCOM000052124D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Dunn, HP: AUTHOR [+2]

Abstract

A high-charge storage one-device random-access memory (RAM) cell struct alleviates cell sensing problems and alpha particle soft errors. The cell 10 can be fabricated in a conventional double polysilicon technology.

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High Capacitance RAM Cell using Two Layers of Polysilicon

A high-charge storage one-device random-access memory (RAM) cell struct alleviates cell sensing problems and alpha particle soft errors. The cell 10 can be fabricated in a conventional double polysilicon technology.

The cell 10 may be fabricated as indicated in Figs. 1 and 2, with Fig. 1 being a sectional view and Fig. 2 being a plan view. The sectional view of Fig. 1 is taken along line 1-1 of Fig. 2. Provided within a semiconductor substrate 12, which is preferably made of P/+/ type material, are recessed oxide regions 14 below which may be formed P/+/ channel stop regions 16. An N/+/ diffusion region 18 is formed adjacent to recessed oxide region 14, and a first layer of doped polysilicon is formed over and in a buried contact arrangement with N/+/ region 18 and over recessed oxide region 14. A high dielectric material, e.g., 20 nanometers of silicon nitride or 60 nanometers of tantalum oxide, is then deposited over the first polysilicon layer. The high dielectric material and the first polysilicon layer are suitably etched to form a dielectric layer 20 and a bottom polysilicon plate 22 of a storage capacitor 24 in contact with N/+/ region 18. The edges or side walls of bottom polysilicon plate 22 are then protected with a layer of thermally grown silicon dioxide, and a gate oxide layer 26 is formed on substrate 12.

Disposed over gate oxide layer 26 and high dielectric layer 20 is a second layer of doped polysilicon which is etched to form a field-effect transistor gate electrode 28 over gate oxide layer 26 and a top polysilicon plate 30 over dielect...