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Browse Prior Art Database

Input Buffer Circuit

IP.com Disclosure Number: IPCOM000052127D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Bula, J: AUTHOR [+2]

Abstract

This input buffer circuit provides field effect transistor logic levels in response to bipolar transistor-transistor-logic (TTL) levels and provides reliable transitions between output levels for both the least positive up level (LPUL) and the most positive down level (MPDL) input signals by the use of a voltage shift circuit for LPULs and a level-sensing trigger circuit for MPDLs.

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Input Buffer Circuit

This input buffer circuit provides field effect transistor logic levels in response to bipolar transistor-transistor-logic (TTL) levels and provides reliable transitions between output levels for both the least positive up level (LPUL) and the most positive down level (MPDL) input signals by the use of a voltage shift circuit for LPULs and a level-sensing trigger circuit for MPDLs.

Devices T1-T3 and C1 provide a buffer circuit between TTL input CS and the gates of T4 and T5. T3 acts as a current source, and T2 as a voltage source such that the voltage at node A is Vt CS-V, where Vt is the threshold voltage of T2 and V is the TTL low input level. The voltage at node B varies between Vt and Vt CS (high) - CS (low). Devices T4-T7 and C2 act as a buffer for the MPDL, which may exceed the threshold voltage of a single grounded source input device. The series connection of T4 and T5 provides a voltage divider such that the potential on node C will be above ground. T5 will not conduct to discharge output node D until the voltage on node B exceeds the threshold voltage of T5 plus the voltage on node C. Output signals may be taken from the gate or source of T6, as required.

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