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LSSD Testable J/K Flip/Flop

IP.com Disclosure Number: IPCOM000052128D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Gretchev, V: AUTHOR

Abstract

A J/K flip-flop which is LSSD (Level Sensitive Scan Design) testable is described. This J/K flip-flop is composed of a number of shift register latches (SRLs) which serve dual purposes, namely, as substitutes for the gates normally used to implement a J/K flip-flop and also to permit the feedback paths of the flip-flops to be broken, removing the sequential nature of the device, to permit combinatorial testing in conformity with LSSD test guidelines by individual exercising of the AND gates, for instance, by computerized testing programs.

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LSSD Testable J/K Flip/Flop

A J/K flip-flop which is LSSD (Level Sensitive Scan Design) testable is described. This J/K flip-flop is composed of a number of shift register latches (SRLs) which serve dual purposes, namely, as substitutes for the gates normally used to implement a J/K flip-flop and also to permit the feedback paths of the flip- flops to be broken, removing the sequential nature of the device, to permit combinatorial testing in conformity with LSSD test guidelines by individual exercising of the AND gates, for instance, by computerized testing programs.

Fig. 1 depicts a standard prior art J/K flip-flop. Fig. 2 depicts the implementation of a J/K flip-flop by shift register latches described in this article.

In normal operation as a J/K flip-flop, clock inputs 1, 2, 3, and 4 are held active. In this situation the circuitry enclosed in boxes G, H, I and J in Fig. 2 forms the equivalent of the circuitry in like-lettered boxes of Figure 1. The result is a circuit which responds as a normal J/K flip-flop.

Considering the testing of a chain of flip-flops forming a register, the tester has available clock inputs 1, 2, 3 and 4 of all J/K flip-flops in addition to the normal clock inputs and scan-in, scan-out lines of the shift register latches (not shown for clarity).

The shift register latches are exercised by selectively deactivating clock inputs 1, 2, 3, and 4 to open feedback paths, F(p), thus permitting combinatorial checking of circuit components to a...