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Multiprocessor Locking with a Bypass for Channel References

IP.com Disclosure Number: IPCOM000052149D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Drimak, EG: AUTHOR [+4]

Abstract

In a multiprocessing system, it is sometimes necessary to prevent references by one processor to data that is currently being modified by another processor. For example, if a processor can retry the execution of an instruction due to a machine malfunction and, in so doing, restores data modified by that to its previous value, the changed data should not be visible to other processors until the successful conclusion of the instruction modifying that data.

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Multiprocessor Locking with a Bypass for Channel References

In a multiprocessing system, it is sometimes necessary to prevent references by one processor to data that is currently being modified by another processor. For example, if a processor can retry the execution of an instruction due to a machine malfunction and, in so doing, restores data modified by that to its previous value, the changed data should not be visible to other processors until the successful conclusion of the instruction modifying that data.

Fig. 1 illustrates a two-processor system consisting of processors A and B, their I/O channels, and their data caches A and B. In such a system, it is often preferred that channel data operations function directly between the channel or its data buffers and memory rather than the other processor's cache. The cache directory design illustrated in Fig. 2 provides a mechanism that will prevent one processor from referencing data currently being modified in the other processor's cache, will allow channel references to that data without delays that might create an I/O overrun problem and, also, permit channel operations between the channels and memory in the preferred manner.

The cache directory shown in Fig. 2 works in a conventional manner to address data in a cache. A lock latch is associated with each group of N pages in each cache. A lock latch is set whenever one of the N pages is modified during the execution on that processor of an instruction that modifies memory data. (Refer to OR gate 2 and Lock jet Controls 5 in Fig. 2.) Special control signal 1 is also provided to set lock latches during a read operation (AND gate 1). Any lock lat...