Browse Prior Art Database

Hermetic Seal Process for Multilevel Metallurgy

IP.com Disclosure Number: IPCOM000052157D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bartush, TA: AUTHOR [+3]

Abstract

Hermetically sealed, multilevel metallurgy for integrated circuits is provided using quartz layers that are thinner than the metal lands. Quartz layer 1 is deposited on substrate 2 to about one half the thickness of metal layer 3 (Fig. 1). A planarizing layer 4 of photoresist is applied such that the ratio of the thickness delta 2 to delta 1 is larger than it would be if quartz layer 1 was of equal thickness to metal layer 3 (Fig. 2).

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Hermetic Seal Process for Multilevel Metallurgy

Hermetically sealed, multilevel metallurgy for integrated circuits is provided using quartz layers that are thinner than the metal lands. Quartz layer 1 is deposited on substrate 2 to about one half the thickness of metal layer 3 (Fig. 1). A planarizing layer 4 of photoresist is applied such that the ratio of the thickness delta 2 to delta 1 is larger than it would be if quartz layer 1 was of equal thickness to metal layer 3 (Fig. 2).

The resist and the portions 5 of quartz which are on top of metal layer 3 are then etched by reactive ion etching in CF(4) and O(2) to remove portions 5 and leave a layer of photoresist 6 on quartz layer 1 (Fig. 3). Accordingly, quartz layer 1 is not subjected to the etching process. The remaining resist is stripped, (Fig.
4), and the process is continued with the deposition of an insulating layer, such as polyimide.

This process does not require a high etch rate ratio of resist to quartz, the quartz layer deposition is thinner and more easily controlled, and the quartz layer is not subjected to the etching process so that the heremetic seal at the edge of the chip is better.

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