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Lightly Doped Source Drain FET Structure

IP.com Disclosure Number: IPCOM000052168D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Critchlow, DL: AUTHOR [+5]

Abstract

An optimum design for the lightly doped drain field-effect transistor (LDDFET) structure, shown in the figure, has been made for an 8.5 V power supply. The design parameters for the structure are as follows: Tox (thickness of the silicon dioxide gate insulator) = 45 nm 1n/-/ (n/-/ length from channel to n/+/) = 0.3 mu m L (minimum channel length) = 1.2 mu m X(j) (n/-/ junction depth) = 0.3 mu m N(D) (peak n/-/ concentration at the Si-SiO(2) interface) = 1.2 x 10/17/ cm/-3/ N(A) (peak acceptor concentration at the Si-SiO(2) interface in the channel) = 1.0 x 10/16/ cm/-3/ rho (substrate resistivity) = 5 ohm-cm V(T) (threshold voltage) = 1 volt.

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Lightly Doped Source Drain FET Structure

An optimum design for the lightly doped drain field-effect transistor (LDDFET) structure, shown in the figure, has been made for an 8.5 V power supply. The design parameters for the structure are as follows:
Tox (thickness of the silicon dioxide gate insulator) = 45 nm 1n/-/ (n/-/ length from channel to n/+/) = 0.3 mu m L (minimum channel length) = 1.2 mu m X(j) (n/-/ junction depth) = 0.3 mu m
N(D) (peak n/-/ concentration at the Si-SiO(2) interface) = 1.2 x 10/17/ cm/-3/

N(A) (peak acceptor concentration at the Si-SiO(2) interface in the channel) = 1.0 x 10/16/ cm/-3/ rho (substrate resistivity) = 5 ohm-cm

V(T) (threshold voltage) = 1 volt.

The characteristics and performance projections of the optimized LDD MOSFET are discussed in S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow and J. F. Shepard, "Design and Characteristics of the Lightly Doped Drain- Source (LDD) Insulated Gate Field-Effect Transistor" IEEE Trans. Electron Devices ED27, 1359-1367 (August 1980).

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