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High Speed, High Density Bipolar Technology

IP.com Disclosure Number: IPCOM000052182D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 122K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

The following steps describe a method for fabricating high-speed, high-performance bipolar circuit components. In particular, a method is described for fabricating high-performance bipolar NPN transistors, Schottky diodes with P guard rings, and resistors with approximately 400 ohms/ sheet resistance.

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High Speed, High Density Bipolar Technology

The following steps describe a method for fabricating high-speed, high- performance bipolar circuit components. In particular, a method is described for fabricating high-performance bipolar NPN transistors, Schottky diodes with P guard rings, and resistors with approximately 400 ohms/ sheet resistance.

Wafer processing up to and including formation of the recessed oxide isolation (ROI) 10, as shown in Fig. 1, is the same as in a conventional process technology. In this regard, it should be noted that, as shown in Fig. 1, the silicon nitride serving as a mask during ROI growth has been etched away. In addition, by using a photoresist mask, phosphorus was selectively ion-implanted to obtain the Nreach-through region 11, as shown in Fig. 1. Thereafter, the usual thin SiO(2) layer was removed, leaving the thick ROI 10 practically unaffected. Then through chemical vapor deposition (CVD), an approximately 1.1 Mum thick SiO(2) layer 12 is obtained and, through the use of a photoresist mask and reactive ion etching (RIE) using CF(4), patterns are formed in the SiO(2) layer 12, as shown in Fig. 1.

Using the SiO(2) layer 12 patterns as a mask and a suitable energy level and dose, oxygen is ion-implanted into the exposed silicon so that the projected range (R(p)) is nominally in the plane of the (upper) out-diffused junction of the subcollector 4 in the N/-/ epi region 8. Then, an approximately 800 Angstrom thick thermal SiO(2) layer 16 is obtained at the exposed N epi surface, and once again using the thick SiO(2) patterns 12 as a mask, and a suitable dose, e.g., approximately 1.5 X 10/14/ cm/-2/ at approximately 50 KeV and approximately 2 X 10/-13/ cm at approximately 150 KeV, boron is ion-implanted. The implanted oxygen and boron, respectively, form buried SiO(2) patterns 14 and P type regions 18 above them, as shown in Fig. 2.

Then, through CVD, an approximately 1.5 K Angstrom thick Si(3)N(4) layer 20 1 K Angstrom thick SiO(2) layer 22 are obtained, as shown in Fig. 3. By using a photoresist mask and CF(4) RIE, patterns are etched in the SiO(2) layer and exposed Si(3)N(4) layer 20. Thereafter, an approximately 1.3 Mum thick polysilicon layer 24 is deposited (e.g., by CVD) and a 2-3 Mum thick coat of photoresist (or some other suitable material like a polyimide, etc.) is formed so as to realize an essential planar top surface.

Using RIE and suitable RIE agents which have an etch rate for the photoresist or other material (of the last described step) which is equal to or slightly less than that for polysilicon, polysilicon patterns are formed isolated by SiO(2) layer 12, as shown in Fig. 3. Then, using a suitable dose and low energy, nitrogen is ion-implanted and the device is annealed to obtain an approximately 500 Angstrom thick layer 26 of Si(3)N(4) at the polysilicon surface. Using buffered HF, the SiO(2) layer 12 is etched away and, using a block-out photoresist mask, boron is ion-implanted...