Browse Prior Art Database

Compact NPN Transistor

IP.com Disclosure Number: IPCOM000052183D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 122K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for realizing very compact NPN transistors using self-aligned metal emitter and appropriately doped polysilicon with a top layer of tungsten silicide to establish contacts to the collector and base.

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Compact NPN Transistor

A method is described for realizing very compact NPN transistors using self- aligned metal emitter and appropriately doped polysilicon with a top layer of tungsten silicide to establish contacts to the collector and base.

The method starts with growing about 3500 Angstroms thick thermal SiO(2) on p- substrate 2. Using photolithography, windows are formed in this SiO(2) layer and an N/+/ dopant is diffused into the exposed silicon to form "subcollector" regions 4, as shown in Fig. 1. About 4800 Angstroms thick therma SiO(2) is grown next and the N/+/ dopant is diffused in the exposed silicon to form "subisolation" regions 6. The P/+/ dopant is driven in and after removal of all SiO(2), a 1-2 Mum thick film of N/-/ type epitaxial silicon 8 is grown on the substrate.

About 1000 Angstroms thick thermal growth of SiO(2) layer 10 is followed by chemical vapor deposition (CVD) of 1000 Angstroms of Si(3)N(4) (not shown). Usi photolithography, the Si(3)N(4), SiO(2)10 and about 3500 Angstrom deep silicon a successively etched. About 8000 Angstroms thick thermal SiO(2) 12 is now grown the exposed silicon regions, as shown in Fig. 1. After stripping the remnant Si(3)N(4), an N/+/ impurity is selectively ion-implanted using a photoresist mask to, realize "collector reach-through" regions 13. An approximately 1200 Angstrom thick layer 14 of Si(3)N(4) is next deposited. The transistor structure at this stage of processing is shown in Fig. 1.

Using photolithography, Si(3)N(4) layer 14 and SiO(2) layer 10 are successively etched, preferably through reactive ion etching (RIE). An approximately 5000 Angstroms thick layer of polysilicon 15 is deposited and, using a photoresist mask 16, a suitable dose of an N/+/ impurity is selectively ion- implanted in the polysilicon 15. Fig. 2 shows this photo-resist mask 16 explicitly. A new photoresist mask 17 is then introduced, as shown in Fig. 3, this mask being used for selective ion-implantation of a suitable dose of a P/+/ impurity.

Thereafter, an approximately 2000 Angstroms thick layer of a suitable refractory metal, e.g., tungsten, is obtained on the surface of the polysilicon layer 15 and a silicide 18, e.g., tungsten silicide, is subsequently formed at the polysilicon surface. About 1000 Angstrom thick layers of SiO(2) 19 and Si(3)N(4) 20 each are next realized above the silicide layer.

The above process step is followed by successive, selective RIE of Si(3)...