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High Density, High Performance Bipolar Technology

IP.com Disclosure Number: IPCOM000052184D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is described for fabricating high-density, high-performance NPN transistors, diffused P resistors and Schottky barrier diodes.

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High Density, High Performance Bipolar Technology

A method is described for fabricating high-density, high-performance NPN transistors, diffused P resistors and Schottky barrier diodes.

As represented in the figures, the formation of N/+/ subcollector regions 4, P/+/ subisolation regions 6, recessed oxide isolation (ROI) regions 12 and N/+/ collector reach-through regions 14 is carried out in the same manner as in conventional bipolar technology. Fig. 1 shows the cross-sections of the beginnings of NPN transistors, P resistors and Schottky barrier diodes as formed according to conventional bipolar technology steps while Fig. 8 shows the completed devices according to the described method. The P/-/ region 2 is the starting substrate, and the N/-/ region 8 is the 1-2 Mum thick epitaxial silicon film.

Using photolithography, the Si(3)N(4) layer 16 and SiO(2) layer 10 are now selectively etched, preferably using reactive ion etching (RIE). Through chemical vapor deposition (CVD), about a 1 Mum thick SiO(2) layer 18 is deposited. Using a photoresist mask and RIE, islands are then formed in SiO(2) layer 18 with practically vertical sidewalls, as shown in Fig. 2.

Using suitable RIE agents (e.g., argon/chlorine), exposed portions of the N/-/ epi region 8 are etched in a controlled manner up to the upper interface of the outdiffused N/+/ subcollectors 4. With SiO(2) island regions 18 and ROI island regions 12 serving as masks, a suitably heavy dose of oxygen is now ion- implanted at the surface of the exposed epi. After annealing, SiO(2) regions 20 are formed where oxygen was ion-implanted earlier; the device cross-sections at this stage of processing are depicted in Fig. 3.

Next, an approximately 1.8 Mum thick layer of in situ P-doped polysilicon 22 is deposited. This is followed by the application of a coat of photoresist (or some other suitable viscous material such as polyimide) so that the top surface of this viscous layer is practically planar. This material is such that its etch rate in the subsequent RIE step is equal to, or slightly less than, that of polysilicon 22.

Using RIE, the planarizing material and the protrusions of the polysilicon 22 into it are etched so that polysilicon patterns isolated by SiO(2) islands 18 are realized. The next process step consists of ion-implantation of a suitable dose of nitrogen. Subsequent annealing results in the formation of Si(3)N(4)layer 23 at the top surface of polysilicon protrusions 22. Fig. 4 shows the device cross- sections at this stage. Using a wet etchant (e.g., BHF), SiO(2) layer 18 is now etched away.

P type intrinsic base regions 24 of the NPN transistors are next formed. This is done by ion-implantation of a suitable dose of a P type dopant, e.g., boron, at a suitable depth beneath the exposed silicon surface. A non-critical, block-out photoresist mask is used during this ion-implantation. Fig. 5 shows the P regions
24.

CVD is then used to form about 0.8 Mum thick SiO(2) layer 2...