Browse Prior Art Database

Preventive Cast Out Operations in Cache Hierarchies

IP.com Disclosure Number: IPCOM000052201D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Bazlen, D: AUTHOR [+3]

Abstract

In storage hierarchies with a high-speed buffer (cache 1) interposed between the main storage (basic storage module (BSM)) and processor, modification of the stored data is often performed according to the "store in cache" principle, in which only the cache block is changed but not its replica in main storage. The change is noted by a change bit in column 3 of cache directory 2. The main storage block is updated only when its cache block is to be overwritten by a new block following a cache miss; in such a case, the modified cache block has to be written back into main storage before the respective cache area can be released. Thus, access to the new cache block which caused a cache miss is delayed by this "cast-out" operation into main storage.

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Preventive Cast Out Operations in Cache Hierarchies

In storage hierarchies with a high-speed buffer (cache 1) interposed between the main storage (basic storage module (BSM)) and processor, modification of the stored data is often performed according to the "store in cache" principle, in which only the cache block is changed but not its replica in main storage. The change is noted by a change bit in column 3 of cache directory 2. The main storage block is updated only when its cache block is to be overwritten by a new block following a cache miss; in such a case, the modified cache block has to be written back into main storage before the respective cache area can be released. Thus, access to the new cache block which caused a cache miss is delayed by this "cast-out" operation into main storage.

It is proposed to eliminate this delay by preventive cast-outs of modified cache blocks into main storage when the processor is in one of its inevitable wait states (e.g., during pending I/O operations). Whenever the processor is not busy, a special microroutine scans cache directory 2 for cache blocks with the change bit being "ON", beginning with the first block eligible for overwriting; in the example shown in the figure, an LRU directory 4 selects the least recently used (LRU) cache block for replacement. Whenever a modified block has been detected during the scan (AND gate 5), it is written back into main storage (by inserting the block address into address register...