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Error Detection for all Errors in a 9 Bit Memory Chip

IP.com Disclosure Number: IPCOM000052208D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kelleher, DF: AUTHOR

Abstract

Five memory chips that each have a 9-bit data bus are combined to store a memory word of 32 data bits and 8 error correction code (ECC) bits for conventional single error correction and double error detection. Four chips each hold 8 data bits and, in addition, hold one parity bit for these 8 data bits. One chip holds the 8 ECC bits and, in addition, holds a parity bit for the ECC bits. The ECC logic is combined with parity logic to detect any combination of errors on a single 9-bit chip.

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Error Detection for all Errors in a 9 Bit Memory Chip

Five memory chips that each have a 9-bit data bus are combined to store a memory word of 32 data bits and 8 error correction code (ECC) bits for conventional single error correction and double error detection. Four chips each hold 8 data bits and, in addition, hold one parity bit for these 8 data bits. One chip holds the 8 ECC bits and, in addition, holds a parity bit for the ECC bits.

The ECC logic is combined with parity logic to detect any combination of errors on a single 9-bit chip.

The ECC logic alone detects these errors. If a single chip multi-bit error occurs, a pattern of syndrome bits will be produced. Howe certain combinations of single chip multi-bit errors appear falsely as a correctable single error. The apparent correctable single error is always located in a different chip from the chip with the multi-bit error, and this condition is detected by the fact that a chip with an apparent correctable single error has good parity. (A syndrome pattern for a single correctable error in a chip with bad parity identifies a correctable error.)

The assignment of the 45 memory bits to the code is shown in the following table. The column headings represent the 45 bits of the 5 chips. The row headings represent the syndrome bits. An X in the table signifies that the memory bit of the column heading is combined in an exclusive OR function to form the syndrome bit of the row heading. The parity bit P does not e...