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Browse Prior Art Database

Power On Detector for Switching Regulator

IP.com Disclosure Number: IPCOM000052212D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Sorenson, DF: AUTHOR

Abstract

This detector provides a "Power On" signal, frequently referred to as a "Power On Reset" signal, or "POR", when normal output of the associated switching regulator is available after start up, and for so long thereafter as normal switching operation of the regulator continues.

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Power On Detector for Switching Regulator

This detector provides a "Power On" signal, frequently referred to as a "Power On Reset" signal, or "POR", when normal output of the associated switching regulator is available after start up, and for so long thereafter as normal switching operation of the regulator continues.

Fig. 1 is a block diagram showing the general topology of a switching regulator including the Power On detector circuit. The regulator shown is a DC- to-DC switching regulator which receives unregulated DC IN at terminal 10, and chops the DC input via operation of a transistor or other suitable switch 12 into pulses on line 14. These pulses are converted to AC by a transformer 16 and then to DC pulses by a rectifier 18. The DC pulses are then smoothed by a load filter 20, the output of which is a DC value at output terminal 22. A feedback control loop 24 controls a Pulse-Width Modulator (PWM) circuit 26 which operates switch 12 via control input 28 to modulate the width of the pulses on line 14 and thus provide a regulated output at 22.

The Power On detector circuit includes a peak detector 30 having an input terminal 32 connected to a secondary of transformer 16 so as to detect AC pulses present at the secondary of the transformer and to provide an output at 34 after such pulses have occurred. The signal on line 34 is applied to threshold and reset circuit 36, the output 38 of which is connected to input 40 of a timer circuit 42. In its "up" state, the output on line 38 allows circuit 42 to begin timing, and after a relatively long delay, the output of 42 switches to pr...