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Memory Address Space Expansion

IP.com Disclosure Number: IPCOM000052214D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Brown, AJ: AUTHOR [+3]

Abstract

This memory addressing scheme enables accessing of sequential memory locations via repetitive application of the same memory address. The addressing scheme includes a counter which provides a high-order pointer to storage volumes and is incremented each time an address is repeated so as to apply that address successively to the successive storage volumes. This arrangement is particularly useful for storage of tables of data where successive bytes of data are normally utilized together to form a unit of data.

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Memory Address Space Expansion

This memory addressing scheme enables accessing of sequential memory locations via repetitive application of the same memory address. The addressing scheme includes a counter which provides a high-order pointer to storage volumes and is incremented each time an address is repeated so as to apply that address successively to the successive storage volumes. This arrangement is particularly useful for storage of tables of data where successive bytes of data are normally utilized together to form a unit of data.

An implementation of this scheme is illustrated in the figure. An address bus 10 is connected to apply fourteen address bits to each of four volumes 12, 14, 16, 18 of storage, and a decoder 20 is provided to enable one out of the four storage volumes in accordance with the decoded value of the high-order two bits of the address bus 10.

Thus far described, the addressing scheme defines the fourteen low-order bits of a storage location and the volume in which that storage location resides. To provide the desired enlarged storage address capacity, a two-bit counter 22 is provided to supply, via lines 24, 26, two additional high-order bits to each of the storage volumes 12, 14, 16, 18. Counter 22 is stepped by memory access control line 28. This counter line 28 is common to the section of memory employing the volumes 12, 14, 16, 18 and signals the presence of a valid address on address bus 10. Thus, each time a valid address appears...