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Array Stabilization for Random Access Memory

IP.com Disclosure Number: IPCOM000052223D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Simi, VM: AUTHOR

Abstract

The drawing shows a two-dimensional array of memory cells on a single chip all tied to ground through R(1). Where the voltage across R(1) differs from a reference voltage V(Ref), oscillations are gated to an AC-to-DC converter, the output of which directly varies the chip substrate voltage of the memory.

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Array Stabilization for Random Access Memory

The drawing shows a two-dimensional array of memory cells on a single chip all tied to ground through R(1). Where the voltage across R(1) differs from a reference voltage V(Ref), oscillations are gated to an AC-to-DC converter, the output of which directly varies the chip substrate voltage of the memory.

The array is a static random-access memory, each cell of which comprises cross-coupled FETs. This may be a conventional latching circuit or an improved such circuit as is published in [*].

All array cells are commonly connected through R(1) to ground. The voltage comparator responds to the voltage across R(1) and V(Ref) to produce an output when array current is below a predetermined level. This output signal gates the on-chip oscillator into the AC-to-DC converter.

The converter generates a negative substrate voltage proportional to the duty cycle of its input signal. Thus, a closed loop is established to maintain a predetermined current through the array. The circuit design is such that the substrate voltage acts as a fine control of the thresholds for the field-effect transistors which make up the memory chip. Reference * V. M. Simi, "Very Low Power Random-Access Memory Cell," IBM Technical Disclosure Bulletin 23, 5007-5010 (April 1981).

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