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Fast Settling Sample and Hold Circuit

IP.com Disclosure Number: IPCOM000052241D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

White, DB: AUTHOR

Abstract

Amplifier A2, resistor R3 and holding capacitor CH are connected to for an inverting integrator. When switch S1 is closed, the circuit integrates an error signal which causes the holding capacitor to charge up to the desired level. Since the non-inverting input of amplifier A2 is connected to ground, its output voltage (EO) is equivalent to the voltage stored on the holding capacitor.

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Fast Settling Sample and Hold Circuit

Amplifier A2, resistor R3 and holding capacitor CH are connected to for an inverting integrator. When switch S1 is closed, the circuit integrates an error signal which causes the holding capacitor to charge up to the desired level. Since the non-inverting input of amplifier A2 is connected to ground, its output voltage (EO) is equivalent to the voltage stored on the holding capacitor.

In order to reduce the exponential settling time of the integrator circuit, error amplifier circuitry is provided. Amplifier A1 and its associated feedback resistors R1 and R2 amplify the difference between the output voltage (EO) and the input voltage (EIN) by a factor of R2/R1.

Since the error signal to the inverting integrator is multiplied by R2/R1, the exponential settling time constant of the sample and hold circuit is then divided by a factor of R2/R1.

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