Browse Prior Art Database

Dynamic Address Translator for I/O Channels

IP.com Disclosure Number: IPCOM000052245D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 5 page(s) / 97K

Publishing Venue

IBM

Related People

Capowski, RS: AUTHOR [+4]

Abstract

The pipelined Channel Dynamic Address translation (CDAT) mechanism described herein can be shared by multiple channels in a time divided and pipelined manner. It contains a 4096 entry Translation Lookaside Buffer (TLB) table having sufficient capacity to hold a translation entry per subchannel, and is designed to provide time interleaved handling of storage access requests received at different input ports of the mechanism. Consequently, a delay in translation associated with any one of the ports affects only channels associated with that port and not channels associated with other ports.

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Dynamic Address Translator for I/O Channels

The pipelined Channel Dynamic Address translation (CDAT) mechanism described herein can be shared by multiple channels in a time divided and pipelined manner. It contains a 4096 entry Translation Lookaside Buffer (TLB) table having sufficient capacity to hold a translation entry per subchannel, and is designed to provide time interleaved handling of storage access requests received at different input ports of the mechanism. Consequently, a delay in translation associated with any one of the ports affects only channels associated with that port and not channels associated with other ports.

The subject CDAT mechanism includes a request/address pipeline, a TLD table and associated translation control hardware. The CDAT is positioned serially in the storage access path of one or more I/O channel processors. In the contemporary channel system environment exemplified in Fig. 1 (extracted from U.S. Patent 4,115,854), the subject mechanism is positioned in a Channel Bus Controller (CBC) unit, as shown in Fig. 2, between plural Channel Bus Assembly Registers (CBARs) and an input buffer array (IN BFR). Each CBAR connects to the output of a multi-channel I/O processor (IOP) or "director" (abbreviated DIR), and the IN BFR interfaces with system main storage. The IN BFR contains several buffer spaces per director/CBAR.

Referring to Fig. 3, the basic operation of the subject CDAT network assumes protocols and timing disclosed in the above-mentioned patent, with the following additions: 1) On storage access requests requiring address translations,
i.e., requests for fetching Indirect Data Address Words (IDAWs), Channel Command Words (CCWs), data and Channel Address Words (CAWs), and requests for storing data and Channel Status Words (CSWs), the associated unit address is presented to the CDAT input port at address tag time. 2) Three control lines, designating Virtual or Real, Control or Data, and Director mode or Channel mode, are also variously pulsed at address tag time.

Each TLB entry consists of multiple bit terms designated STO, STE, PTE, key, virtual-real address pair(s) for data requests, virtual-real address pair(s) for control requests, use and valid bits, as described below: STO (SEGMENT TABLE ORIGIN). Address in storage of the beginning of a segment table (also called segment table address (STA)) * . STE (SEGMENT TABLE ENTRY). Contains length and starting address of page table * . PTE (PAGE TABLE ENTRY). Contains high-order bits of the real address which replace (in the translation process) the high-order bits of a logical address in the formation of a real address * . KEY. Storage protection key associated with a real address.

USE BIT. Used by TLB controls to lock a TLB entry during translation.

VALID BIT. Indicates presence of a useful entry in the TLB position so marked.

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Inputs to the TLB address register are formed by a unit address (8 bits) supplied with the channel reques...