Browse Prior Art Database

High Speed Bipolar Data Transmission System

IP.com Disclosure Number: IPCOM000052247D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Abramson, P: AUTHOR

Abstract

This article describes a data transmission system capable of speeds up to 12 megabits per second using bipolar transmission techniques. Arbitrarily, positive pulses will be used to stand for 1's and negative pulses for 0's. Both the transmitter and the receiver are transformer coupled at their respective ends of the transmission lines for the elimination of the common mode noise and to avoid a common ground loop. The system utilizes the polar RZ format and requires can input clock and an NRZ data signal. At the receiver, the clock signal is extracted from transmitted data and the polar RL signal is decoded.

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High Speed Bipolar Data Transmission System

This article describes a data transmission system capable of speeds up to 12 megabits per second using bipolar transmission techniques. Arbitrarily, positive pulses will be used to stand for 1's and negative pulses for 0's. Both the transmitter and the receiver are transformer coupled at their respective ends of the transmission lines for the elimination of the common mode noise and to avoid a common ground loop. The system utilizes the polar RZ format and requires can input clock and an NRZ data signal. At the receiver, the clock signal is extracted from transmitted data and the polar RL signal is decoded.

Fig. 1 illustrates eleven pulse trains that explain the operation of the system. Line 1 shows the supplied clock signal, and line 2 shows a standard non-return to zero (NRZ) code. Line 3 shows the clocked locations of the 1's, and line 4 shows the inverted N~Z signal from line 2. Line 5 illustrates the clocked 0's occurring in line 4. Line 6 illustrates the polar RZ code using bipolar pulses to transmit the data as it appears on lines 3 and 5.

Line 7 illustrates the 1's, and line 8 the 0's as received at a receiver. Line 9 illustrates the clocking frequency extracted by the summation of the signals appearing on lines 7 and 8, and line 10 illustrates a clock signal like line 9 but delayed 1/2 of a clock pulse width. The NRZ data line 11 is reconstructed by comparing the delayed clock signal in line 10 against the 1's and 0's in lines 7 and 8.

Fig. 2 illustrates a schematic diagram of a transmitter and receiver for generating the signals shown in Fig. 1. NRZ data is inputted on line 1, and the clock information on line 2. Inverter 3 and AND gate 4 are used to gate transistor 5 to drive the transformer...