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Four Phase Decoder for Data/Clock Separator

IP.com Disclosure Number: IPCOM000052248D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Henning, LR: AUTHOR [+4]

Abstract

A data/clock separator for magnetic data recording defines window times with overlapping pulses to avoid false decoding due to variable circuit delays.

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Four Phase Decoder for Data/Clock Separator

A data/clock separator for magnetic data recording defines window times with overlapping pulses to avoid false decoding due to variable circuit delays.

In Fig. 1, CLK is a conventional master timing signal derived from an oscillator during data writing, or locked to recorded clock signals during data reading. Overlapping DATA WINDOW and CLOCK WINDOW signals are produced by circuit 20 of Fig. 2, along with signals T0, T1, ..., T7, marking different bit times in an 8-bit data byte.

In Fig. 2, every negative edge of CLK reverses the state of latch 21, whose true output Q is the DATA WINDOW signal. D-type latch 22 is triggered by the positive edges of CLK, and its data input responds to the complementary output Q of latch 21 to produce the CLOCK WINDOW signal. Shift register 23 is initialized at the beginning of each data byte by a conventional RESET BYTE signal. Thereafter, DATA WINDOW shifts a bit through register 23 to form the T0, T1, ..., T7 outputs. T7 is returned to the data input.

Fig. 3 shows a circuit 30 for glitch-free decoding of the first quarter of a bit time, such as bit number one (T1). Latch 31 is set by the previous bit, T0, and reset by CLOCK WINDOW. AND gate 32 combines the true output of latch 31 with the current bit time, T1, to produce a signal T1:1 representing the first quarter of T1. Circuit 40 (Fig. 4) decodes the fourth quarter of bit number one. AND gate 41 sets latch 42 when both CLOCK WINDOW a...