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Dedicated Addresses Control Interrupt Functions for Multiple I/O Devices

IP.com Disclosure Number: IPCOM000052251D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Nicholson, JO: AUTHOR

Abstract

Separate logic mean in each of number different I/O interfaces respond to the same bus addresses for interrupt handling. These addresses are decoded in addition to the unique I/O device addresses for each interface. Cycle-steal (direct memory access) may be performed in this way also.

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Dedicated Addresses Control Interrupt Functions for Multiple I/O Devices

Separate logic mean in each of number different I/O interfaces respond to the same bus addresses for interrupt handling. These addresses are decoded in addition to the unique I/O device addresses for each interface. Cycle-steal (direct memory access) may be performed in this way also.

Microprocessor 1 uses storage data and address busses 11 for all storage devices (not shown), and a combined data/address bus 12 for I/O devices. Control-signal bus 13 specifies the meaning and direction of the contents of bus
12. A single interrupt input 14 is pulled down by any I/O device to request an interrupt. Input 15 similarly indicates a cycle-steal request.

I/O device 2 contains a decoder 21 for recognizing four events on busses 12 and 13: read data from address FE (R'FE'); read data from address FF (R'FF'); write data to address FE (W'FE'); and write data to address FF (W'FF'). Other decoded outputs 211 provide individual addresses to device adapter hardware 22 for initiating data transfers to and from bus 12 over lines 221. Decoder 21 connects lines 221 to bus 12 via gate 24 at the proper times. Adapter 22 requests service by a signal on interrupt line 222. Logic 23 responds to signal 222 and to the outputs of decoder 21 to pull down processor interrupt line 14 via AND output 231 and to produce a properly timed signal on line 232, which is connected to one data bit (e.g., DB) of I/O bus 12. Other I/O devices, such as 3, are similar, except that line 332 is connected to a different data bit of bus 12 (e.g., bit Dl for device 3). Each device has a wire-OR connection to processor interrupt input 14 via lines 231, 331, etc.

Microprocessor 1 performs the following sequence: (a) write a byte to I/O ...