Browse Prior Art Database

Variable Speed I/O Instructions

IP.com Disclosure Number: IPCOM000052253D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 4 page(s) / 140K

Publishing Venue

IBM

Related People

Crooks, TL: AUTHOR [+2]

Abstract

Control circuitry for channel control logic is responsive to the decode of the port address specified by the I/O instruction for generating either normal or fast-rate synchronizing signals for use during the execution of the I/O instruction. I/O devices having different speed requirements of limitation are accommodated by loading the appropriate port address into a work register which is used for I/O instructions to particular I/O devices. The channel control logic decodes the port address to determine the appropriate execution speed. By this arrangement, no special lines are required from the I/O device attachments to select the speed of execution.

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Variable Speed I/O Instructions

Control circuitry for channel control logic is responsive to the decode of the port address specified by the I/O instruction for generating either normal or fast- rate synchronizing signals for use during the execution of the I/O instruction. I/O devices having different speed requirements of limitation are accommodated by loading the appropriate port address into a work register which is used for I/O instructions to particular I/O devices. The channel control logic decodes the port address to determine the appropriate execution speed. By this arrangement, no special lines are required from the I/O device attachments to select the speed of execution. A port address of zero indicates that the I/O instruction will be executed at normal speed, and a port address other than zero determines that the I/O instruction will be executed at high speed. While the setup time for normal and fast I/O instructions is the same, the execution portion of the fast I/O instruction is approximately 3 to 16 times faster than that for the normal I/O instruction.

I/O device attachments requiring the normal I/O instruction speed, as illustrated in Fig. 2, receive the strobe 1 signal over line 14 of Fig. 1. I/O attachments for I/O devices executing I/O instructions at the faster speed are connected to line 15 to receive strobe 2. An I/O attachment could use both strobe 1 and strobe 2 to control an I/O device or devices for executing I/O instructions at either normal or fast speed.

The microcode in control storage (not shown) for supporting particular I/O devices is written appropriately to accommodate the I/O instruction execution speed required by the device or devices. Prior to execution of the I/O instruction, a general work register, and in this instance WR 0 LO in local storage register (LSR) stack 1, used to identify port address and device address, is loaded via the microcode with a port address of zero for normal I/O instruction execution speeds or with port address other than zero for I/O instructions to be executed at the fast speed. The port and device addresses are moved from the preloaded general work register, WR 0 LO, through Storage Gate :LO 2 and over line 3 and via input gate 8 into channel data buffer 4. Channel control logic 16 decodes the port and device addresses. The Control Out signal generated by channel control logic on line 11 informs the I/O device attachments that the device address is available on Data Bus Out (DBO) 5. If the port address has a value of zero, the Control Out signal has a duration...