Browse Prior Art Database

Predetermined Counters

IP.com Disclosure Number: IPCOM000052280D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Krol, PG: AUTHOR

Abstract

A microprocessor controls the modulus and rate of a predetermined count by using a two-section counter, a primary and a vernier counter. The vernier counter counts a basic period of time, while the primary counter counts multiples of that time.

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Predetermined Counters

A microprocessor controls the modulus and rate of a predetermined count by using a two-section counter, a primary and a vernier counter. The vernier counter counts a basic period of time, while the primary counter counts multiples of that time.

A microprocessor will preset a register for determining a modulus of the vernier counter. The microprocessor supplies a reset signal through the OR circuit "0" to enable the AND circuit "A" to transfer the signal contents of the register to the vernier counter. The system clock, which times the microprocessor, also activates the vernier counter to count down towards zero. As the vernier counter counts past zero, it emits a borrow signal to again enable AND circuit "A" for transferring the contents in the register to the vernier counter. Accordingly, the vernier counter acts as a free-running counter operating at the system clock rate, but having a predetermined value fed in by the microprocessor to the register.

The primary counter for counting a predetermined time period is preset via Preset-1 from the microprocessor. Each time a borrow is emitted by the vernier counter, the primary counter counts one. When the primary counter has counted past zero, it supplies interrupt signal to the microprocessor, indicating the end of the count cycle.

Additionally, a decoder (not shown) may be added to the primary counter for indicating intermediate counts to the processor. In response to such intermediate count...