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Browse Prior Art Database

Memory Access Control Circuit

IP.com Disclosure Number: IPCOM000052295D
Original Publication Date: 1981-May-01
Included in the Prior Art Database: 2005-Feb-11
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Ko, MA: AUTHOR

Abstract

Normally available asynchronous signals are converted to memory access signals synchronized to a clock for permitting only one user access to a memory at any one time.

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Memory Access Control Circuit

Normally available asynchronous signals are converted to memory access signals synchronized to a clock for permitting only one user access to a memory at any one time.

In certain applications, such as the sharing of a time ported memory by a dual ported display adapter and a processor, it is necessary to generate a single fixed length pulse synchronized to a clock from an asynchronous signal. In this set up, the processor can access the memory at the rising edge of the clock for as long as the clock is high. The display accesses the memory at the falling edge of the clock for as long as the clock is low. Each time the processor requires access to the memory it is important to ensure that access is permitted only in the cycle dedicated to the processor, and that no more accesses will be repeated in the cycles yet to come. Otherwise, the possibility exists that the memory will be accessed when the processor signals are changing.

Referring to the circuit, in the quiescent state when there is no processor memory access, the input to flip-flop 1 is low. As such, the output along line 2 is also low, which clears flip-flop 3 and causes the output along line 4 to be high. If the processor needs to access the memory, the data input to flip-flop 1, which detects this condition based on an input along line 5, will be high. Along line 5 are applied various combinational logic inputs based on addresses, I/O enable, and read and write signals. At...